1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more specifically to a static random access memory (SRAM) array having a super supply voltage.
2. Description of the Prior Art
The design and manufacture of SRAM devices which are free of design and reliability problems is a challenging task. It is not uncommon for SRAM arrays to be fraught with hard failures and reliability problems, especially when first silicon of a new SRAM device is tested. Therefore, it is standard practice to test SRAM devices for "hard" functional failures, as well as propensities to reliability problems. Such device testing is critical for identifying, analyzing, and correcting problem areas early.
Traditional testing methods typically use a nominal memory array supply voltage, such as VCC at 5 volts, to perform diagnostic and reliability testing. While testing at 5 volts often identifies functional failures, this voltage level makes it difficult to accelerate and thus identify failures that are caused by latent defects. Often such defects are not identified and corrected until much time has been expended in performing reliability tests such as the Infant Life test which can take hundreds of hours. Additionally, using traditional testing methods, it is difficult to identify latent failures, which may not show until later, resulting in high failure-in-time (FIT) rates.